The present invention relates to network switching and, more particularly, to time shared use of common receive FIFO structure in a data network switch logic chip.
A data network switch permits data communication among a plurality of media stations in a local area network. Data frames, or packets, are transferred between stations by means of data network switch media access control (MAC) circuitry at each switch port. The MAC supervises transmission of data traffic from the port to the network, the reception of data traffic at the port from the network, and mediates data traffic at the port to avoid collisions. Transmit and receive FIFO buffers at each port are coupled to the MAC to hold frame data temporarily.
The network switch passes data frames received from transmitting stations to destination stations based on the header information in the received data frames. The header information in each received frame may identify a single destination or contain a virtual destination address that identifies multiple destinations to which the frame data are to be transmitted. In the latter case, copies of the frame data are output to a plurality of ports associated with the destination stations. In a broadcast transmission mode, all stations on the network are to receive the frame data. Frame data can also be transmitted to a destination in another network, which is indicated by a VLAN destination address.
Depending upon mode of operation, an incoming frame, temporarily held in a receive FIFO, may be moved to memory external to the switch for later transmission or placed in the transmit FIFO of the appropriate port for immediate transmission out to the network. The receive FIFO passes frame header information to a rules checker that will identify the appropriate output MAC port(s) for the frame data. The rules checker, which contains information to map destination addresses to MAC ports, may be embodied in a switch logic chip or located externally to the chip.
The receive FIFO for each port thus is capable of holding incoming data, while sending header information data to the rules checker for identification of the transmission output ports, and transferring the held data to external memory for subsequent transmission to the network. The FIFO at each port must contain sufficient register capacity and control circuitry to perform this functionality. As switch development has evolved, the switch logic elements have been integrated into a single chip. In order to provide greater traffic flow capacities and increased number of switch ports in the service of increasingly robust data networks, the need for efficient use of chip architecture becomes critical. The number of MACs and FIFOs required increases with each additional port. The storage capacity of each FIFO, as well as the control logic therefor, must also be increased as traffic flow control becomes more complex.
A description of the increased MAC complexity and its resulting demand on chip architecture is contained in the aforementioned commonly assigned copending application, Ser. No. 08/992,921. That problem is addressed by providing one combinational logic and register arrangement for executing similar MAC functions for the plurality of switch ports. The common circuitry, which primarily performs logic operations, at any given time is appropriately associated with the respective port for which MAC functions are required.
The time shared common MAC circuitry described in the aforementioned application frees up chip space by eliminating similar elements at each port that would provide redundant functionality. The need remains for increasing the efficient use of receive FIFO resources. The FIFOs must store and transfer increasingly larger volumes of communication data, which demand a greater proportion of chip area. An effort to improve efficiency of chip allocation to FIFO resources would present challenges that include managing a potentially constant stream of data from all ports that must be appropriately bufferred and transferred without overflow or loss. The transfer of data out of the FIFO must occur in periods during which new data is being received from MAC ports. Consolidation of FIFO architecture to meet these needs would involve precise determination of different levels of data flow capacities among various elements of the FIFO structure. Accurate timing of various stages of FIFO control, with some functions occurring concurrently, would be required for the orderly flow of data. FIFO functions are complicated by the need to transfer frame data both to external memory and to a rules checker for mapping the frame data to appropriate switch output ports.
The present invention addresses the above noted needs and drawbacks of current network switches in part by providing a single receive FIFO for a plurality of ports of the multiport switch so that redundant duplication of FIFO structure at each port is eliminated. Data received at each port is transferred to the FIFO on a time shared basis, each port having a designated time slot in a complete sequence of clock cycles. This staged input pipeline to the receive FIFO is synchronized to a sufficiently high clock rate to effectively handle the received data. The invention thus provides more efficient use of chip resources and architecture space than prior art conventional devices.
Another aspect of the invention involves a receive FIFO structure having a single port RAM, for storing network communication data received from each port of the switch. The RAM is connected to a FIFO control unit, which is coupled to a MAC for each port by a MAC bus, by a FIFO memory input bus. Writing of data received from each port via the MAC bus to the RAM is controlled on a time shared basis. In an alternative embodiment, the MAC bus may be coupled to a shared media access control circuitry such as disclosed in the above-identified copending application.
The FIFO control unit includes a receive RAM interface that is connected to the MAC bus for receiving communication data from the ports and to the FIFO memory input bus for transferring communication data to the RAM for temporary storage. As the FIFO memory input bus has a larger bit transfer capacity than the MAC bus, the receive RAM interface can accumulate incoming data during clock cycles in which data is being read from the single port RAM. When the accumulated data for a given port is to be written to the RAM in a subsequent write cycle, it is then combined with additional incoming data for the same port received at that time for transfer to the RAM.
The FIFO control unit is coupled to the RAM by a FIFO memory output bus for transferring data read from the RAM to first and second slave state machines in the FIFO control unit. The first slave state machine receives frame data for output over a data bus to external memory. The second slave state machine receives frame header information data for output over a rules checker bus to a rules checker. The memory output bus has a significantly larger bit transfer capacity than the data bus and the rules checker bus, whereby data can concurrently be transferred by both state machines to the external memory and the rules checker. The transfer of data out from the state machines can take place during both write and read cycles of the single port RAM because of the large bit transfer capacity of the memory output bus. As this capacity is also larger than the FIFO memory input bus to the RAM, the likelihood of RAM data overflow is minimized.
Additional advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiment of the invention is shown and described, simply by way of illustration of the best mode contemplated of carrying out the invention. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.